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Invasive BCI Chip Design

Book references

The bibliography from the original technical chapters, presented in a readable format. Citation details are reproduced from the source material.

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  1. U. Chaudhary, N. Birbaumer, and A. Ramos-Murguialday, "Brain–computer interfaces for communication and rehabilitation," Nature Reviews Neurology, vol. 12, no. 9, pp. 513-525, 2016.
  2. L. Kuhlmann, K. Lehnertz, M. P. Richardson, B. Schelter, and H. P. Zaveri, "Seizure prediction—ready for a new era," Nature Reviews Neurology, vol. 14, no. 10, pp. 618-630, 2018.
  3. G. Schalk and E. C. Leuthardt, "Brain-computer interfaces using electrocorticographic signals," IEEE reviews in biomedical engineering, vol. 4, pp. 140-154, 2011.
  4. E. C. Leuthardt, G. Schalk, J. Roland, A. Rouse, and D. W. Moran, "Evolution of brain-computer interfaces: going beyond classic motor physiology," Neurosurgical focus, vol. 27, no. 1, p. E4, 2009.
  5. H. Wu, J. Chen, X. Liu, W. Zou, J. Yang, and M. Sawan, "An Energy-Efficient Small-Area Configurable Analog Front-End Interface for Diverse Biosignals Recording," IEEE Transactions on Biomedical Circuits and Systems, 2023.
  6. I. H. Stevenson and K. P. Kording, "How advances in neural recording affect data analysis," Nature neuroscience, vol. 14, no. 2, pp. 139-142, 2011.
  7. C. M. Lopez et al., "A Neural Probe with Up to 966 Electrodes and Up to 384 Configurable Channels in 0.13um SOI CMOS," IEEE transactions on biomedical circuits and systems, vol. 11, no. 3, pp. 510-522, 2017.
  8. E. Musk, "An integrated brain-machine interface platform with thousands of channels," Journal of medical Internet research, vol. 21, no. 10, p. e16194, 2019.
  9. C. M. Lopez and X. Huang, "Circuits and Architectures for Neural Recording Interfaces," in Biomedical Electronics, Noise Shaping ADCs, and Frequency References: Advances in Analog Circuit Design 2022: Springer, 2023, pp. 45-57.
  10. A. Bagheri, M. T. Salam, J. L. P. Velazquez, and R. Genov, "Low-frequency noise and offset rejection in DC-coupled neural amplifiers: A review and digitally-assisted design tutorial," IEEE transactions on biomedical circuits and systems, vol. 11, no. 1, pp. 161-176, 2016.
  11. R. R. Harrison and C. Charles, "A low-power low-noise CMOS amplifier for neural recording applications," IEEE Journal of solid-state circuits, vol. 38, no. 6, pp. 958-965, 2003.
  12. J. Xu, S. Mitra, C. Van Hoof, R. F. Yazicioglu, and K. A. Makinwa, "Active electrodes for wearable EEG acquisition: Review and electronics design methodology," IEEE reviews in biomedical engineering, vol. 10, pp. 187-198, 2017.
  13. B. Gosselin, M. Sawan, and C. A. Chapman, "A low-power integrated bioamplifier with active low-frequency suppression," IEEE Transactions on biomedical circuits and systems, vol. 1, no. 3, pp. 184-192, 2007.
  14. K. A. Ng and P. K. Chan, "A CMOS analog front-end IC for portable EEG/ECG monitoring applications," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2335-2347, 2005.
  15. R. Muller, S. Gambini, and J. M. Rabaey, "A 0.013${\hbox {mm}}^{2} $, 5$\mu\hbox {W} $, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply," IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 232-243, 2011.
  16. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, 1996.
  17. T. Denison, K. Consoer, W. Santa, A.-T. Avestruz, J. Cooley, and A. Kelly, "A 2 $\mu\hbox{W}$ 100 nV/rtHz Chopper-Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field Potentials," IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2934-2945, 2007, doi: 10.1109/jssc.2007.908664.
  18. C.-Y. Wu, C.-H. Cheng, and Z.-X. Chen, "A 16-channel CMOS chopper-stabilized analog front-end ECoG acquisition circuit for a closed-loop epileptic seizure control system," IEEE transactions on biomedical circuits and systems, vol. 12, no. 3, pp. 543-553, 2018.
  19. E. Greenwald et al., "A Bidirectional Neural Interface IC With Chopper Stabilized BioADC Array and Charge Balanced Stimulator," IEEE Trans Biomed Circuits Syst, vol. 10, no. 5, pp. 990-1002, Oct 2016, doi: 10.1109/TBCAS.2016.2614845.
  20. B. Gosselin, "Recent advances in neural recording microsystems," Sensors, vol. 11, pp. 4572-4597, 2011.
  21. B. Razavi, Design of analog CMOS integrated circuits. 清华大学出版社有限公司, 2005.
  22. M. S. Chae, W. Liu, and M. Sivaprakasam, "Design optimization for integrated neural recording systems," IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 1931-1939, 2008.
  23. D. De Dorigo et al., "Fully immersible subcortical neural probes with modular architecture and a delta-sigma ADC integrated under each electrode for parallel readout of 144 recording sites," IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3111-3125, 2018.
  24. H. Chandrakumar and D. Marković, "A 15.2-ENOB 5-kHz BW 4.5-$\mu $ W Chopped CT $\Delta\Sigma $-ADC for Artifact-Tolerant Neural Recording Front Ends," IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3470-3483, 2018.
  25. S. Pavan, R. Schreier, and G. C. Temes, Understanding delta-sigma data converters. John Wiley & Sons, 2017.
  26. J. Chen, M. Tarkhan, H. Wu, F. H. Noshahr, J. Yang, and M. Sawan, "Recent trends and future prospects of neural recording circuits and systems: A tutorial brief," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2654-2660, 2022.
  27. F. Hashemi Noshahr, M. Nabavi, and M. Sawan, "Multi-channel neural recording implants: A review," sensors, vol. 20, no. 3, p. 904, 2020.
  28. D.-Y. Yoon, S. Pinto, S. Chung, P. Merolla, T.-W. Koh, and D. Seo, "A 1024-channel simultaneous recording neural SoC with stimulation and real-time spike detection," in 2021 Symposium on VLSI Circuits, 2021: IEEE, pp. 1-2.
  29. C. M. Lopez et al., "An implantable 455-active-electrode 52-channel CMOS neural probe," IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 248-261, 2013.
  30. S.-Y. Park et al., "A miniaturized 256-channel neural recording interface with area-efficient hybrid integration of flexible probes and CMOS integrated circuits," IEEE Transactions on Biomedical Engineering, vol. 69, no. 1, pp. 334-346, 2021.
  31. N. S. K. Fathy, J. Huang, and P. P. Mercier, "A digitally assisted multiplexed neural recording system with dynamic electrode offset cancellation via an LMS interference-canceling filter," IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 953-964, 2021.
  32. J. P. Uehlin, W. A. Smith, V. R. Pamula, S. I. Perlmutter, J. C. Rudell, and V. S. Sathe, "A 0.0023 mm $^ 2$/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression," IEEE transactions on biomedical circuits and systems, vol. 14, no. 2, pp. 319-331, 2019.
  33. N. Pérez-Prieto, Á. Rodríguez-Vázquez, M. Álvarez-Dolado, and M. Delgado-Restituto, "A 32-channel time-multiplexed artifact-aware neural recording system," IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 5, pp. 960-977, 2021.
  34. M. Sharma, H. J. Strathman, and R. M. Walker, "Verification of a rapidly multiplexed circuit for scalable action potential recording," IEEE transactions on biomedical circuits and systems, vol. 13, no. 6, pp. 1655-1663, 2019.
  35. C. Kim, S. Joshi, H. Courellis, J. Wang, C. Miller, and G. Cauwenberghs, "Sub-$\mu $ V rms-Noise Sub-$\mu $ W/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging," IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3101-3110, 2018.
  36. H. Kassiri et al., "Rail-to-rail-input dual-radio 64-channel closed-loop neurostimulator," IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2793-2810, 2017.
  37. S. Zhao, C. Fang, J. Yang, and M. Sawan, "Emerging energy-efficient biosignal-dedicated circuit techniques: A tutorial brief," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2592-2597, 2022.
  38. S. Gibson, J. W. Judy, and D. Marković, "Spike sorting: The first step in decoding the brain: The first step in decoding the brain," IEEE Signal processing magazine, vol. 29, no. 1, pp. 124-143, 2011.
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  41. X. Liu et al., "A fully integrated wireless compressed sensing neural signal acquisition system for chronic recording and brain machine interface," IEEE Transactions on biomedical circuits and systems, vol. 10, no. 4, pp. 874-883, 2016.
  42. T. Wu, W. Zhao, H. Guo, H. H. Lim, and Z. Yang, "A streaming PCA VLSI chip for neural data compression," IEEE transactions on biomedical circuits and systems, vol. 11, no. 6, pp. 1290-1302, 2017.
  43. T. E. Özkurt et al., "High frequency oscillations in the subthalamic nucleus: a neurophysiological marker of the motor state in Parkinson's disease," Experimental neurology, vol. 229, no. 2, pp. 324-331, 2011.
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  45. M. X. Cohen, Analyzing neural time series data: theory and practice. MIT press, 2014.
  46. J. Yoo, L. Yan, D. El-Damak, M. A. B. Altaf, A. H. Shoeb, and A. P. Chandrakasan, "An 8-channel scalable EEG acquisition SoC with patient-specific seizure classification and recording processor," IEEE journal of solid-state circuits, vol. 48, no. 1, pp. 214-228, 2012.
  47. L. Guo, D. Rivero, J. Dorado, J. R. Rabunal, and A. Pazos, "Automatic epileptic seizure detection in EEGs based on line length feature and artificial neural networks," Journal of neuroscience methods, vol. 191, no. 1, pp. 101-109, 2010.
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  50. K. Abdelhalim, H. M. Jafari, L. Kokarovtseva, J. L. P. Velazquez, and R. Genov, "64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator," IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2494-2510, 2013, doi: 10.1109/jssc.2013.2272952.
  51. Y. Wei et al., "A review of algorithm & hardware design for AI-based biomedical applications," IEEE transactions on biomedical circuits and systems, vol. 14, no. 2, pp. 145-163, 2020.
  52. S.-A. Huang, K.-C. Chang, H.-H. Liou, and C.-H. Yang, "A 1.9-mW SVM processor with on-chip active learning for epileptic seizure control," IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 452-464, 2019.
  53. L. Feng, Z. Li, and Y. Wang, "VLSI design of SVM-based seizure detection system with on-chip learning capability," IEEE transactions on biomedical circuits and systems, vol. 12, no. 1, pp. 171-181, 2017.
  54. M. A. B. Altaf, C. Zhang, and J. Yoo, "A 16-channel patient-specific seizure onset and termination detection SoC with impedance-adaptive transcranial electrical stimulator," IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2728-2740, 2015.
  55. M. A. B. Altaf and J. Yoo, "A 1.83$\mu $ J/classification, 8-channel, patient-specific epileptic seizure classification SoC using a non-linear support vector machine," IEEE Transactions on Biomedical Circuits and Systems, vol. 10, no. 1, pp. 49-60, 2015.
  56. K. Abdelhalim, V. Smolyakov, and R. Genov, "Phase-synchronization early epileptic seizure detector VLSI architecture," IEEE transactions on biomedical circuits and systems, vol. 5, no. 5, pp. 430-438, 2011.
  57. M. Shoaib, K. H. Lee, N. K. Jha, and N. Verma, "A 0.6–107 µW energy-scalable processor for directly analyzing compressively-sensed EEG," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 4, pp. 1105-1118, 2014.
  58. K. H. Lee and N. Verma, "A low-power processor with configurable embedded machine-learning accelerators for high-order and adaptive analysis of medical-sensor signals," IEEE Journal of Solid-State Circuits, vol. 48, no. 7, pp. 1625-1637, 2013.
  59. M. Shoaran, B. A. Haghi, M. Taghavi, M. Farivar, and A. Emami-Neyestanak, "Energy-efficient classification for resource-constrained biomedical applications," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 4, pp. 693-707, 2018.
  60. U. Shin et al., "NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3243-3257, 2022.
  61. B. Zhu, M. Farivar, and M. Shoaran, "Resot: Resource-efficient oblique trees for neural signal classification," IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 4, pp. 692-704, 2020.
  62. J. Yang and M. Sawan, "From seizure detection to smart and fully embedded seizure prediction engine: A review," IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 5, pp. 1008-1023, 2020.
  63. G. K. Anumanchipalli, J. Chartier, and E. F. Chang, "Speech synthesis from neural decoding of spoken sentences," Nature, vol. 568, no. 7753, pp. 493-498, 2019.
  64. J. Liu et al., "4.5 BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring," in 2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, vol. 64: IEEE, pp. 62-64.
  65. S. Zhao et al., "A 0.99-to-4.38 uJ/class Event-Driven Hybrid Neural Network Processor for Full-Spectrum Neural Signal Analyses," IEEE Transactions on Biomedical Circuits and Systems, 2023.
  66. V. J. Lawhern, A. J. Solon, N. R. Waytowich, S. M. Gordon, C. P. Hung, and B. J. Lance, "EEGNet: a compact convolutional neural network for EEG-based brain–computer interfaces," Journal of neural engineering, vol. 15, no. 5, p. 056013, 2018.
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  68. F. Tian, J. Yang, S. Zhao, and M. Sawan, "NeuroCARE: A generic neuromorphic edge computing framework for healthcare applications," Frontiers in Neuroscience, vol. 17, p. 1093865, 2023.
  69. C. Wang, J. Yang, and M. Sawan, "NeuroSEE: A Neuromorphic Energy-Efficient Processing Framework for Visual Prostheses," IEEE Journal of Biomedical and Health Informatics, vol. 26, no. 8, pp. 4132-4141, 2022.
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  71. C. Fang, C. Wang, S. Zhao, F. Tian, J. Yang, and M. Sawan, "A 510μW 0.738-mm2 6.2-pJ/SOP Online Learning Multi-Topology SNN Processor with Unified Computation Engine in 40-nm CMOS," IEEE Transactions on Biomedical Circuits and Systems, 2023.
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